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  2. emulation quadrature and h bridge signals fpga enable hil simulation
  3. Emulation of quadrature and H-bridge signals on an FPGA to enable HiL simulation

Emulation of quadrature and H-bridge signals on an FPGA to enable HiL simulation

This project is about developing FPGA code for hardware-in-the-loop simulation, namely an inverse PWM signal generator and inverse encoder signal counter. Two modules have been developed: one of the modules reads a PWM signal and determines the duty cycle of the signal. The other module has angular data as input and generates quadrature signals to emulate an encoder.

The inverse PWM module has no detectable error, and the inverse encoder has an error below 1 in 100,000 pulses. As such, it is suitable for a digital twin setup, using hardware-in-the-loop simulation.